Upscale AI Challenges Nvidia’s Dominance with SkyHammer Scale-Up Fabric

For decades, the architecture of high-performance computing has been defined by a fundamental tension between proprietary innovation and the industry’s desire for universal standards. In the era of the central processing unit, every major manufacturer developed its own distinct, highly proprietary methods for linking multiple processors into shared memory clusters. Despite the noble efforts of organizations like the CCIX consortium and the CXL consortium to create a "universal glue" that would allow various CPUs to function as a single, massive compute resource, the reality of the market remained largely fragmented.

These attempts to standardize Symmetric Multiprocessing (SMP) and Non-Uniform Memory Access (NUMA) largely failed to gain universal traction for a simple reason: the practical demand for mixing and matching CPU architectures from different vendors within a single shared-memory domain was remarkably small. Furthermore, hardware vendors found that they could innovate on their SMP and NUMA chipsets—which eventually moved from discrete components to being embedded directly onto the silicon—at a cadence independent of their core designs or I/O subsystems. By avoiding the slow, committee-driven process of a standards body, these companies could differentiate their products and push features to market as they saw fit.

Today, the industry finds itself at a similar crossroads, though the focus has shifted from the CPU to the GPU and the broader category of "XPUs" (accelerated processing units). The current industry term for this specialized interconnectivity is "scale-up networking," and the market’s hope for a standard version remains as resilient as ever. This optimism is driven by the fundamental economic law of substitution; markets crave competition to drive down costs, and nowhere is that cost-containment more necessary than in the high-stakes world of artificial intelligence infrastructure.

The current landscape is dominated by Nvidia, which charges a significant premium for its NVSwitch and NVLink ports. These technologies provide the unparalleled bandwidth and low latency required to link as many as 72 GPUs into a cohesive shared memory system, exemplified by the company’s NVL72 rack-scale machines. While Nvidia has recently shown some flexibility through its NVLink Fusion initiative—allowing custom CPU makers and hyperscalers to integrate NVLink ports into their own silicon—it maintains a tight grip on the ecosystem. To date, Nvidia has not allowed customers to combine their own CPUs and XPUs within an NVSwitch environment without maintaining a heavy reliance on the Nvidia protocol and licensing.

However, the tide may be shifting. As AI workloads evolve, particularly in the realm of inference, the industry is looking for alternatives that offer the scale-up capabilities of NVLink without the proprietary lock-in. This is the vacuum that Upscale AI intends to fill.

Upscale AI, a startup that has rapidly moved from stealth to a major industry player, recently raised the curtain on its plans for a new generation of scale-up and scale-out networking. Since its initial funding rounds, the company has seen its valuation double to $2 billion, backed by $500 million in total capital. Its workforce has expanded to over 300 employees, led by a management team with deep roots in high-performance systems. Executive chairman Rajiv Khemani and CEO Barun Kar bring decades of experience to the table, positioning the company as a serious contender to Nvidia’s networking hegemony.

The centerpiece of Upscale AI’s strategy is the "SkyHammer" scale-up switch ASIC. While the company has been cautious with specific "speeds and feeds," recent disclosures provide a glimpse into the raw power of the silicon. SkyHammer boasts an aggregate bandwidth of 115.2 terabits per second (Tb/sec), a figure that puts it on equal footing with the most advanced scale-out network ASICs currently offered by industry titans like Broadcom, Cisco Systems, and Nvidia itself. Furthermore, the SkyFabriX architecture supported by these chips is designed to eventually reach aggregate bandwidths measured in multiple petabits per second.

Achieving this level of performance typically requires ganging multiple ASICs together within a single switch chassis. This is a common practice among vendors like Broadcom and Meta, where a two-tier internal network is created using multiple independent ASICs to effectively double the port bandwidth. While this approach can increase latency for certain port hops, it offers a cost-effective way to scale performance without waiting for the next generation of single-chip designs. Upscale AI appears to be following a similar economic logic, aiming to deliver high-density connectivity that balances performance with the practicalities of street pricing and manufacturing costs.

In terms of scalability, the SkyHammer architecture is designed to support up to 576 accelerators within a single networking tier. By utilizing multiple tiers, the company claims the fabric can scale to "thousands of accelerators," likely targeting benchmarks such as 1,024 or 1,156 units. This puts SkyHammer in direct competition with the UALink consortium, which is currently promising support for 1,024 XPUs in a single tier. For comparison, Nvidia’s upcoming "Rubin Ultra" generation is expected to push NVSwitch limits to 1,152 GPUs through multi-tier configurations, though its current production focus remains on the 72-GPU domain.

When analyzing the raw bandwidth math, SkyHammer presents an interesting trade-off. At 576 devices, each accelerator receives approximately 200 Gb/sec of bandwidth. This is significantly lower than the 1.8 TB/sec offered by Nvidia’s NVLink 5 on Grace-Blackwell systems, or the projected 3.6 TB/sec for the Vera-Rubin generation. Even at a smaller scale of 72 XPUs, SkyHammer delivers roughly 1.6 Tb/sec per port, which translates to 200 GB/sec of memory bandwidth—about one-sixth of the throughput of the current NVSwitch 5 stack.

However, Upscale AI argues that for many AI workloads, particularly inference, sheer bandwidth is not the only metric that matters. Arvind Srikumar, Senior Vice President of Product and Marketing at Upscale AI, emphasizes that predictable latency and jitter are the true keys to performance in the token-generation phase of AI models.

"With AI, the latency has to be super predictable, and we have built into the ASIC predictable jitter," Srikumar explained. He noted that while standard protocols provide link-level reliability, Upscale AI has developed internal mechanisms to ensure the fabric remains 100 percent lossless. By starting with a "clean sheet of paper" rather than retrofitting existing Ethernet protocols, the company believes it can offer a level of parallelism and reliability that traditional Ethernet fabrics lack.

This "clean sheet" approach is particularly relevant as the industry debates the merits of UALink over Ethernet (UALoE) and the ESUN memory protocols. SkyHammer is fundamentally an Ethernet switch ASIC at its core, running UALoE rather than a native, non-Ethernet version of UALink. While some had hoped for a dedicated, high-radix switch that could run UALink natively, the decision to stick with Ethernet reflects the broader market trend. Many industry veterans believe that Ethernet will eventually displace InfiniBand as the dominant fabric for AI, provided it can close the gap on port-to-port hop latency.

In a strategic move that highlights the complexity of the AI ecosystem, Upscale AI has actually partnered with Nvidia for its scale-out requirements. The company will acquire Nvidia’s Spectrum-X ASICs to build its own scale-out switches. These will run Upscale AI’s "SkyOS" network operating system, an AI-optimized version of the SONiC (Software for Open Networking in the Cloud) platform originally created by Microsoft. SONiC has become a de facto standard for hyperscalers, and by porting SkyOS to Spectrum-X, Upscale AI ensures that its software stack can manage both scale-up and scale-out networks through a single, unified telemetry and orchestration tool called SkyCMD.

This software-led approach is intended to give customers the freedom to mix and match CPUs, GPUs, and XPUs from various vendors, front-ended by any NIC or DPU. The challenge, however, remains Nvidia’s refusal to support SkyHammer as a legitimate alternative to NVSwitch for its own GPUs. As it stands, there is no official path for users to perform scale-up networking with Nvidia hardware using Upscale AI’s fabric.

This standoff creates a unique opportunity for other silicon providers. AMD, for instance, is increasingly reliant on third-party scale-up options to support its UALink and ESUN initiatives. Some industry observers suggest that AMD might eventually seek to acquire a company like Upscale AI to secure its own scale-up networking technology and capture more of the value chain.

As the AI market continues to expand, the battle over the "glue" that binds these massive clusters together will only intensify. Nvidia may eventually be forced to choose between maintaining its proprietary walls or adapting its NVLink protocol to run on third-party hardware like SkyHammer to remain the dominant supplier in an increasingly standardized world. For now, the industry watches as Upscale AI attempts to prove that a predictable, lossless, and open Ethernet fabric can indeed compete with the most expensive and exclusive interconnects on the market.