For decades, the architecture of high-performance computing has been defined by a fundamental tension between proprietary innovation and the industry’s desire for universal standards. In the era of the central processing unit, every major manufacturer developed its own distinct, highly proprietary methods for linking multiple processors into shared memory clusters. Despite the noble efforts of organizations like the CCIX consortium and the CXL consortium to create a "universal glue" that would allow various CPUs to function as a single, massive compute resource, the reality of the market remained largely fragmented.
These attempts to standardize Symmetric Multiprocessing (SMP) and Non-Uniform Memory Access (NUMA) largely failed to gain universal traction for a simple reason: the practical demand for mixing and matching CPU architectures from different vendors within a single shared-memory domain was remarkably small. Furthermore, hardware vendors found that they could innovate on their SMP and NUMA chipsets—which eventually moved from discrete components to being embedded directly onto the silicon—at a cadence independent of their core designs or I/O subsystems. By avoiding the slow, committee-driven process of a standards body, these companies could differentiate their products and push features to market as they saw fit.
Today, the industry finds itself at a similar crossroads, though the focus has shifted from the CPU to the GPU and the broader category of "XPUs" (accelerated processing units). The current industry term for this specialized interconnectivity is "scale-up networking," and the market’s hope for a standard version remains as resilient as ever. This optimism is driven by the fundamental economic law of substitution; markets crave competition to drive down costs, and nowhere is that cost-containment more necessary than in the high-stakes world of artificial intelligence infrastructure.
The current landscape is dominated by Nvidia, which charges a significant premium for its NVSwitch and NVLink ports. These technologies provide the unparalleled bandwidth and low latency required to link as many as 72 GPUs into a cohesive shared memory system, exemplified by the company’s NVL72 rack-scale machines. While Nvidia has recently shown some flexibility through its NVLink Fusion initiative—allowing custom CPU makers and hyperscalers to integrate NVLink ports into their own silicon—it maintains a tight grip on the ecosystem. To date, Nvidia has not allowed customers to combine their own CPUs and XPUs within an NVSwitch environment without maintaining a heavy reliance on the Nvidia protocol and licensing.
However, the tide may be shifting. As AI workloads evolve, particularly in the realm of inference, the industry is looking for alternatives that offer the scale-up capabilities of NVLink without the proprietary lock-in. This is the vacuum that Upscale AI intends to fill.

Upscale AI, a startup that has rapidly moved from stealth to a major industry player, recently raised the curtain on its plans for a new generation of scale-up and scale-out networking. Since its initial funding rounds, the company has seen its valuation double to $2 billion, backed by $500 million in total capital. Its workforce has expanded to over 300 employees, led by a management team with deep roots in high-performance systems. Executive chairman Rajiv Khemani and CEO Barun Kar bring decades of experience to the table, positioning the company as a serious contender to Nvidia’s networking hegemony.
