For decades, the architecture of high-performance computing was defined by a fiercely guarded isolationism. Every major CPU manufacturer developed its own proprietary methods for linking multiple processors into shared memory clusters. Whether through SMP (Symmetric Multiprocessing) or NUMA (Non-Uniform Memory Access) designs, these interconnects were the "secret sauce" that allowed a handful of chips to act as a single, cohesive unit. Despite the noble efforts of industry groups like the CCIX consortium and the more recent CXL (Compute Express Link) consortium to create a universal "glue" for silicon, the dream of a vendor-neutral, high-performance interconnect has largely remained elusive.
The failure to establish a truly universal CPU standard stemmed from a simple market reality: customers rarely had a reason to mix and match different CPU architectures within a single shared memory domain. Furthermore, proprietary designs allowed vendors to innovate on their own schedules. They could refine their SMP and NUMA chipsets—which were eventually integrated directly into the silicon—at a pace independent of core designs or I/O advancements. Most importantly, being untethered from a standards body meant they could differentiate their products exactly as they saw fit, maintaining a competitive moat that was difficult for rivals to cross.
However, as the industry pivots from general-purpose CPU computing to the era of massive AI clusters, the conversation around interconnects is shifting. The industry is now searching for a standard version of what is effectively a NUMA interconnect for GPUs and XPUs—what the industry has rebranded as "scale-up networking." This renewed interest in standardization is driven by the fundamental economic law of substitution and a desperate market desire for competition to drive down the astronomical costs of AI infrastructure.
At the center of this tension is Nvidia. The company currently commands a significant premium for its proprietary NVSwitch and NVLink ports. These technologies provide the unparalleled bandwidth and low latency required to bind as many as 72 GPUs into a single shared memory system, which Nvidia markets as the NVL72 rackscale machine. While Nvidia has made some concessions through its NVLink Fusion initiative—allowing custom CPU and XPU makers to add NVLink ports to their devices—it remains a tightly controlled ecosystem. Currently, Nvidia does not allow customers to combine their own CPUs and XPUs using NVSwitches and licensed NVLink protocols to build independent shared memory systems.
The industry’s hope is that an alternative will eventually emerge to challenge this lock-in. This is why Upscale AI has become one of the most watched startups in the semiconductor and networking space. Since its initial $200 million Series A funding round in January, the company has seen its momentum accelerate. Upscale AI has now raised a total of $500 million, seeing its valuation double to $2 billion. Its workforce has also expanded rapidly, now exceeding 300 employees as it prepares to challenge the status quo of AI networking.
This week, the leadership at Upscale AI provided a clearer look at their strategy for both scale-up and scale-out networking. Led by co-founder and executive chairman Rajiv Khemani and CEO Barun Kar—both veterans with deep roots in high-performance systems—the company is positioning its "SkyHammer" ASIC as the cornerstone of a new, more open AI fabric.

While specific "speeds and feeds" for the SkyHammer ASIC remain somewhat guarded, the technical details that have emerged suggest a formidable piece of hardware. SkyHammer is reported to have an aggregate bandwidth of 115.2 Tb/sec. This figure places it on equal footing with the state-of-the-art scale-out network ASICs currently offered by industry giants like Broadcom, Cisco, and Nvidia. Furthermore, the company’s SkyFabriX architecture is designed to eventually support switch gear with aggregate bandwidth measuring in the multiple petabits per second.
Achieving these petabit scales will likely involve ganging multiple SkyHammer ASICs together within a single switch. This is a proven strategy used by companies like Broadcom and Meta, where a "baby two-tier" network can be constructed from six independent ASICs to double the bandwidth of ports. While this approach can increase latency due to additional port hops, it offers a more cost-effective path to massive bandwidth than developing a single, monolithic 2X-bandwidth device. Upscale AI appears to be betting on the economic efficiency of this architecture to provide a competitive alternative to proprietary stacks.
The scalability of the SkyHammer memory domain is equally ambitious. The architecture reportedly supports up to 576 accelerators in a single networking tier. By utilizing multiple tiers, the company claims it can scale to "thousands of accelerators." This is a direct shot at the UALink consortium, which has promised support for 1,024 XPUs in a single tier, and Nvidia, which is aiming to scale its NVSwitch fabric to 1,152 GPUs in the upcoming "Rubin Ultra" generation.
However, a raw comparison of bandwidth reveals a significant gap. At 576 devices, the SkyHammer chip provides approximately 200 Gb/sec of bandwidth per device. This is a fraction of the 1.8 TB/sec offered by the NVLink 5 generation used in Nvidia’s Grace-Blackwell systems, or the 3.6 TB/sec expected in the Vera-Rubin generation. Even at a smaller scale of 72 XPUs, SkyHammer delivers roughly 1.6 Tb/sec per port, which is still about one-sixth the memory bandwidth of the NVSwitch 5 stack.
Upscale AI’s defense of this disparity rests on the belief that bandwidth is not the only metric that matters, especially for AI inference. Arvind Srikumar, Senior Vice President of Product and Marketing at Upscale AI, argues that predictable latency and jitter are the true bottlenecks for token generation in AI models. Srikumar notes that while traditional Ethernet fabrics often rely on a fixed, less-parallel pipeline, SkyHammer was designed from a "clean sheet of paper" to minimize latency and ensure 100 percent losslessness within the fabric.
"One of the most important metrics when it comes to tokens is latency," Srikumar explained. "We have to produce, but this is where it’s a little bit different. With AI, the latency has to be super predictable, and we have built into the ASIC predictable jitter. We have some protocols which are standards-based that provide link-level reliability, but within the fabric, we have a mechanism to ensure the fabric is 100 percent lossless."
This focus on "reliable and predictable latency" suggests that Upscale AI is targeting a specific segment of the market—those running massive inference workloads where the overhead of proprietary, high-bandwidth training fabrics may be overkill. The company is leaning into standards like UALink over Ethernet (UALoE) and the ESUN memory protocols. The fact that SkyHammer utilizes UALoE indicates that, despite its optimizations, it remains an Ethernet-based ASIC at its core.

The strategy becomes even more interesting when looking at Upscale AI’s relationship with Nvidia. In a surprising move, the startup has partnered with its primary rival to use Nvidia’s Spectrum-X Ethernet switches for its scale-out fabrics. This partnership highlights a growing consensus among networking veterans: while InfiniBand remains the gold standard for the absolute lowest port-to-port hop latency in HPC, Ethernet is rapidly catching up and offers superior scalability for the largest AI clusters.
Upscale AI will acquire Nvidia’s Spectrum-X ASICs to build its own scale-out switches. These will be powered by SkyOS, the company’s proprietary network operating system. SkyOS is an AI-optimized evolution of SONiC (Software for Open Networking in the Cloud), the open-source operating system originally created by Microsoft that has become a staple in hyperscaler data centers. By porting SkyOS to run on both its own SkyHammer scale-up switches and Nvidia’s Spectrum-X scale-out hardware, Upscale AI is offering a unified management and telemetry layer through its SkyCMD orchestration tool.
This unified approach allows customers to see their entire scale-up and scale-out network as a single entity. It also promises the freedom to mix and match CPUs, GPUs, and XPUs from different vendors, provided they are front-ended by a compatible DPU or NIC.
The significant hurdle remains vendor support. While the technology is promising, Nvidia has no current incentive to support SkyHammer or SkyOS as a legitimate alternative to its own NVSwitch for scale-up operations. For those heavily invested in the Nvidia ecosystem, the proprietary "walled garden" remains the only path to maximum performance.
However, the landscape looks different for competitors like AMD. Lacking a dominant proprietary switch equivalent to NVSwitch, AMD is increasingly dependent on third-party innovators to provide the scale-up networking required for its own AI accelerators. There is already speculation that if Upscale AI’s technology proves successful in the field, it could become an acquisition target for a company like AMD, looking to secure its own scale-up fabric and diversify its revenue streams.
Ultimately, the battle for the heart of the AI data center will be won by the architecture that can best balance raw performance with economic reality. Nvidia can always choose to increase the radix of its NVSwitch ASICs to flatten its networks, though likely at the cost of bandwidth per port. Alternatively, it could eventually adopt an industry-standard scale-up network for its inference-focused products while keeping training locked down. As the first generation of Ultra Ethernet Consortium-compatible switches nears the market, the long-standing reign of InfiniBand is facing its most serious challenge yet. Whether Upscale AI’s SkyHammer can truly act as the "universal glue" for the next generation of XPUs remains to be seen, but with $500 million in backing and a focus on predictable performance, they are positioned to be a major player in the unfolding AI infrastructure war.
