The Long Road to Open Silicon: How OpenTitan and the Rise of Secure Roots of Trust are Reshaping the Semiconductor Industry

The 2018 Hot Chips conference served as a pivotal moment for the future of hardware security. It was there that Google hardware engineers first pulled back the curtain on "Titan," a custom-designed chip intended to establish a silicon root of trust (RoT) within the company’s massive server fleet. At the time, the semiconductor industry was still reeling from the discovery of the Spectre and Meltdown vulnerabilities, which had exposed fundamental flaws in the way modern processors handle data. The industry was desperate for a new approach to security—one that began at the very base of the hardware stack.

Google’s vision, however, extended beyond its own data centers. The engineers spoke of a future where this technology would be available as an open-source offering, marking a significant milestone in the then-nascent open-silicon movement. Leading this ambitious charge was Dominic Rizzo, who served as the technical lead manager for the effort at Google for five years. Rizzo’s mission was not just to build a secure chip, but to solve a fundamental problem facing cloud providers: the inconsistency of hardware security across a fragmented supply chain.

Reflecting on those early days, Rizzo recalls how he pitched the concept internally. The primary selling point for Google was the realization that their security posture was becoming "lumpy" because they were purchasing a vast array of heterogeneous hardware for their cloud operations. Each vendor had its own proprietary security implementations, making it difficult to maintain a uniform standard across the infrastructure. OpenTitan was conceived as the first truly credible, well-resourced, "do-it-right-from-scratch" open-source silicon project, designed to smooth out those lumps and provide a transparent, verifiable foundation for trust.

For Rizzo, OpenTitan was the beginning of a decade-long journey to push the "open silicon rock" up a very steep hill. After leaving Google in 2023, he transitioned to the role of project director for OpenTitan at lowRISC, the official maintainer and host of the project. That same year, he co-founded zeroRISC, a startup where he now serves as CEO, with the explicit goal of driving broad commercial adoption of open-silicon RoT.

The movement gained significant momentum in May when zeroRISC, alongside industry giants including Qualcomm, Meta, and Analog Devices, as well as the Max Planck Institute for Security and Privacy, launched Pavona. Operating under the auspices of the nonprofit standards consortium GlobalPlatform, Pavona is chaired by Rizzo and functions as a neutral ecosystem for designing secure hardware. The project is modeled after successful open-source software initiatives like the Yocto Project and the Zephyr Project, providing a framework where competitors can collaborate on non-differentiating but critical security components.

Pavona is particularly notable for its focus on the future of encryption. It includes a production-stage post-quantum cryptography (PQC) stack that supports a variety of modern algorithms, such as ML-KEM, ML-DSA, and SLH-DSA. This composable platform allows organizations to build their own hardware roots of trust and chip subsystems with the confidence that they are protected against the emerging threats of the quantum computing era.

The logic behind open silicon mirrors the arguments that propelled open-source software to dominance decades ago. By eliminating the heavy licensing fees and royalties associated with commercial chips from dominant players like Intel, AMD, and Nvidia, companies can significantly reduce costs. Furthermore, the ability to reuse infrastructure and collaborate on shared designs fosters faster innovation. Perhaps most importantly for security, open-source designs offer greater transparency throughout the supply chain. With more eyes on the code and the silicon blueprints, vulnerabilities and defects can be detected and remediated far more quickly than in proprietary "black box" systems.

Despite these clear advantages, the path to open silicon has been far more difficult than the path to open software. Rizzo notes that the idea of open-source silicon emerged roughly at the same time as Linux, but it struggled to gain comparable momentum for years. The challenges are rooted in the highly specialized nature of the semiconductor industry. Unlike software development, where a full-stack engineer might handle various aspects of a project, silicon engineering is siloed into very specific roles.

In the chip world, there are backend production specialists, layout experts, analog engineers, digital designers, and design verification (DV) professionals. This extreme specialization meant that the "leverage it how you will" ethos of open source didn’t naturally take root. Additionally, the sheer number of people capable of designing silicon is a tiny fraction of the global software developer population. Inconsistent interfaces and a lack of standardized design flows further hampered early efforts.

However, the tide has begun to turn, driven by a fundamental shift in how the semiconductor industry operates. According to lowRISC, the widespread adoption of the IP (Intellectual Property) business model has been a primary catalyst. Today’s chip designs are modular, with the vast majority of vendors integrating third-party IP from providers like Arm or Synopsys and relying on foundries like TSMC for manufacturing. This culture of IP reuse has already brought about the cost reductions and quality improvements typically associated with open source. From here, it is a relatively small logical step for silicon vendors to begin substituting proprietary IP with open-source alternatives.

The maturation of the RISC-V architecture has also been a game-changer. Since its introduction in 2010, the open RISC-V instruction set architecture (ISA) has seen broad adoption in embedded systems and is now making a serious push into the data center. Rizzo argues that RISC-V "gave permission" to the industry to think about open source in a hardware context. Once the industry accepted an open-source ISA, the natural next question was: why not an open-source implementation?

This shift in mindset has led to a flurry of activity and real-world implementations. In 2019, lowRISC released the Ibex CPU, which has since been integrated into various System-on-Chip (SoC) designs. More recently, in 2024, Nuvoton brought a discrete RoT security chip to market based on OpenTitan, with Google announcing plans to utilize the chip in Chromebooks running ChromeOS.

The momentum continued into 2025 with the first release of Caliptra, a root-of-trust architecture that incorporates OpenTitan elements. Developed through the CHIPS Alliance and the Open Compute Project, Caliptra counts Microsoft, Google, AMD, and Nvidia among its contributors. It is specifically designed for data-center-level SoCs, proving that open-source security is no longer confined to small embedded devices but is ready for the most demanding computing environments.

The ecosystem is further supported by organizations like the CHERI (Capability Hardware Enhanced RISC Instructions) Alliance, founded in 2024. Membership includes Arm, Google, lowRISC, and the UK National Cyber Security Centre (NCSC). CHERI technology aims to protect data by building security directly into hardware memory, addressing a class of vulnerabilities that have plagued software for decades.

At zeroRISC, the focus is on providing what Rizzo calls a "silicon trust stack." The company’s offerings include the Pavona repository and a collaboration layer for design teams, complete with version control and verification workloads for physical hardware. Their stack includes post-quantum-ready silicon IP and a provisioning service that allows for secure debugging and over-the-air updates for OEMs.

The urgency surrounding Post-Quantum Cryptography cannot be overstated. Rizzo points out that the U.S. government and European regulators have set aggressive deadlines for organizations to transition to PQC. The threat is twofold: the eventual ability of quantum computers to break current standards like AES-256, and the immediate threat of "harvest now, decrypt later." In this scenario, malicious actors steal encrypted data today, intending to decrypt it years from now when quantum technology becomes available. Google has estimated that this "quantum day" could arrive as early as 2029.

Implementing PQC is significantly more complex than classical cryptography. In classical systems, a single "hard problem" typically sits at the root of all operations. In the post-quantum world, the trade-offs are more varied, the underlying mathematical problems are different, and the implementations for various operations are themselves unique. This complexity makes the collaborative, open-source approach of projects like Pavona even more essential.

Looking ahead, the focus of the open-silicon movement is shifting toward sustainability and governance. While the industry has proven it can build the technology in the open, the challenge now lies in building a long-term ecosystem where everyone benefits. This includes navigating new regulatory landscapes, such as the European Union’s Cyber Resilience Act. This legislation is shifting the liability for cyber incidents onto device makers, forcing them to take greater responsibility for their supply chains.

This regulatory shift is making the necessity of a hardware root of trust clear to the broader market. As Rizzo notes, the software attack surface has grown so large that the only way to address it is to have a silicon root of trust beneath the software—a foundation that can be reset to a known good state. Without that control over the chip itself, the battle for security is increasingly seen as a losing one. Through the continued evolution of OpenTitan, Pavona, and the broader open-silicon community, the industry is finally building the tools necessary to secure that foundation.