Upscale AI Unveils SkyHammer Architecture to Challenge Nvidia’s Scale-Up Networking Monopoly

While specific "speeds and feeds" for the SkyHammer ASIC remain closely guarded, the company has revealed that the chip will boast an aggregate bandwidth of 115.2 Tb/sec. This figure places SkyHammer on equal footing with the most advanced scale-out network ASICs currently offered by industry titans like Broadcom, Cisco Systems, and Nvidia. Upscale AI’s SkyFabriX architecture is designed to scale even further, with plans for switch gear that can handle multiple petabits per second of aggregate bandwidth.

Achieving these petabit-scale speeds will likely involve ganging multiple SkyHammer ASICs together within a single switch chassis. This is a proven technique in the networking world; by using a multi-tier internal fabric—often involving specialized fabric connectors similar to the "Ramon" devices used with Broadcom’s Jericho ASICs—manufacturers can double or quadruple the effective bandwidth per port. While this approach can increase latency due to additional internal "hops," it allows for the creation of massive, high-density switches that are more cost-effective than developing a single, gargantuan ASIC.

In terms of scalability, the SkyHammer architecture is designed to support up to 576 accelerators in a single networking tier. By utilizing multiple tiers, Upscale AI claims the fabric can scale to "thousands of accelerators." This puts the company in direct competition with the UALink consortium, which is aiming for 1,024 XPUs in a single tier, and Nvidia’s future "Vera-Rubin" generation, which targets 1,152 GPUs across a multi-tier NVSwitch fabric.

A closer look at the mathematics of SkyHammer’s bandwidth reveals an interesting strategic choice. At a scale of 576 devices, each device would receive approximately 200 Gb/sec of bandwidth. While this is a formidable figure, it is considerably lower than the 1.8 TB/sec offered by Nvidia’s NVSwitch 5 generation in the Blackwell NVL72 systems. When normalized, SkyHammer’s bandwidth per port at a 72-XPU scale is roughly one-sixth that of Nvidia’s current top-tier offering.

However, Upscale AI argues that raw bandwidth is not the only metric that matters, particularly for AI inference workloads. In the world of token generation, predictable latency and the elimination of "jitter" (variance in latency) are often more critical than peak throughput. Arvind Srikumar, senior vice president of product and marketing at Upscale AI, emphasizes that the SkyHammer ASIC was built from a "clean sheet of paper" specifically to address these needs.

"With AI, the latency has to be super predictable, and we have built into the ASIC predictable jitter," Srikumar explained. He noted that while standard Ethernet fabrics are often fixed-pipeline arrangements with limited parallelism, SkyHammer employs a more parallel architecture to minimize latency and ensure a 100 percent lossless fabric. This approach is intended to provide the reliability required for scale-up memory domains without the overhead of traditional Ethernet retrofitting.